Thanks to this cache, each GPU is prevented from having its own VRAM well to have a shared one, which greatly reduces the multiplicity of data and eliminates bottlenecks that are the product of communication in a conventional multi-GPU. In addition, like any last-level cache, it has the ability to give consistency to all the elements that are clients of it.Its bandwidth is much higher than that of HBM memory, which is why it makes use of more advanced 3D interconnection technologies, which allow much higher bandwidths.The chiplet where the last-level cache is located not only stores said memory, but is also where the entire VRAM access mechanism is located, which in this way is decoupled from the rendering engine.The high bandwidth required does not allow conventional interconnections and is therefore only possible in a 2.5DIC configuration.It uses an interposer with a very high speed interface such as a silicon bridge or TSV interconnects to communicate with the L2 cache of each GPU.It is not found in any of the GPUs, but is external to them and therefore is on a separate chip.The latest-level cache for chiplet-based Multi-GPUs brings together a number of common characteristics that are independent of who the manufacturer is, so the following list of characteristics applies to any GPU of this type, regardless of the manufacturer.

Under the new paradigm, the last level cache of each GPU is ignored as memory for Tile Caching and the last level cache of the Multi-GPU is used, which would be found on a separate chip.

What if we decide to apply the same functionality to a chiplet-based GPU? Well, this is where the additional cache level comes in. The problem is that a cache does not work like a conventional memory and at any time and without program control a cache line can be sent to the next level of the memory hierarchy. The advantage of this is that it saves on the energy cost of some graphics operations, but the disadvantage is that it depends on the amount of last-level cache that is in the GPU. The Tile Caching concept began to be used from NVIDIAвЂ™s Maxwell architecture and AMDвЂ™s Vega architecture, it is about taking some concepts from rendering by tiles, but with the difference that instead of rendering each tile in a separate memory and only writing it to the VRAM when it is finished is done on the second level cache. To this we have to add the way in which the graphics cards work when rendering the graphics in 3D in real time, which has caused that the configuration with multiple graphics cards is no longer used. So the data is duplicated as many times as the number of graphics cards involved in rendering, which is grossly inefficient. Ideally, all GPUs working together would have the same VRAM memory well in common, but this is not the case. Of course, at the speed of the PCI Express port, which is a real bottleneck. The limitations of Split Frame Rendering and the potential solutionД®ach GPU contains 2 collections of DMA drives, the first pair can simultaneously read or write data in the system RAM through the PCI Express port, but in many graphics cards with Crossfire or SLI support there is another collection of DMA drives, the which allow access to the VRAM of the other graph. Split Frame Rendering seems an equitable way to distribute the work, however, now we will see what are the problems that this method entails and with what limitations it is. The first stages of the pipeline, prior to rasterization, are carried out exclusively on the first GPU, as for rasterization and the later stages are carried out equally on each GPU. There is another way to render a scene in 3D that is Split Frame Rendering, which consists of several GPUs rendering a single scene and dividing the work, but with the following nuances: a GPU is the master GPU that reads the list of screen and handles the rest.

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